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16-mbit (1m x 16) pseudo static ram cyk001m16zccau mobl3? cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05454 rev. *a revised april 21, 2004 features ? wide voltage range: 2.70v?3.30v ? access time: 55 ns, 70 ns ? ultra-low active power ? typical active current: 3 ma @ f = 1 mhz ? typical active current: 13 ma @ f = f max ? ultra low standby power ? automatic power-down when deselected ? cmos for optimum speed/power ? deep sleep mode ? offered in a 48-ball bga package functional description the cyk001m16zccau is a high-performance cmos pseudo static ram organized as 1m words by 16 bits that supports an asynchronous memory interface. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl) in portable applications such as cellular telephones. the device can be put into standby mode when deselected (ce high or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enables (ce low) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the locati on specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enables (ce low) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . refer to the truth table for a complete description of read and write modes. this device incorporates a low power mode wherein data integrity is not guaranteed, but power consumption reduces to less than 100 w. this mode (deep sleep mode) is enabled by driving zz low.see the truth table for a complete description of read, write, and deep sleep mode. note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 1m 16 ram array i/o0 ? i/o7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o8 ? i/o15 we ble bhe a 16 a 0 a 1 a 9 a 10 power-down circuit bhe ble ce ce a 17 zz a 19 a 18
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 2 of 12 pin configuration [2, 3, 4] fbga we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe nc a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 3 2 6 5 4 1 d e b a c f g h top view a 16 gnd vcc a 18 nc a 19 product portfolio [5] product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max min. typ. [5] max. typ. [5] max. typ. [5] max. typ. [5] max. cyk001m16zccau 2.70 3.0 3.30 55 3 5 13 22 80 150 70 17 note: 2. dnu pins have to be left floating. 3. ball h6 can be used to upgrade to 32m density. 4. nc ?no connect? - not connected internally to the die. 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c.
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 3 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied........... .............. .............. ..... ?55c to + 125c supply voltage to ground potent ial ................. ?0.4v to 4.6v dc voltage applied to outputs in high z state [6, 7, 8] ........................................?0.4v to 3.3v dc input voltage [6, 7, 8] .....................................?0.4v to 3.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range device range ambient temperature v cc cyk001m16zccau industrial ?25c to +85c 2.70v to 3.30v parameter description test conditions cyk001m16zccau -55 cyk001m16zccau -70 uni t min. typ. [5] max. min. typ. [5] max. v cc supply voltage 2.7 3.0 3.3 2.7 3.3 v v oh output high voltage i oh = ?-0.1 ma v cc - 0.4 v cc - 0.4 v v ol output low voltage i ol = 0.1ma 0.4 0.4 v v ih input high voltage v cc = 2.7v to 3.3v 0.8* vcc v cc +0.4v 0.8* vcc v cc +0.4v v v il input low voltage -0.4 0.4 -0.4 0.4 v i ix input leakage current gnd < v in < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 13 22 13 17 ma f = 1 mhz 3 5 3 5 ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ?0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc =3.30v vcc = 3.3v 100 525 100 525 a i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.30v vcc = 3.3v 80 150 80 150 a i zz deep sleep current vcc=vccmax; zz= low 50 50 a notes: 6. v il(min) = -0.5v for pulse durations less than 20ns. 7. v ih(max) = vcc + 0.5v for pulse durations less than 20ns. 8. overshoot and undershoot specifications ar e characterized and are not 100% tested.
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 4 of 12 thermal resistance [9] capacitance [9] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 8 pf c out output capacitance 8 pf parameter description test conditions bga unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedence, per eia / jesd51. 55 c/w jc thermal resistance (junction to case) 17 c/w note: 9. tested initially and after any design or proc ess changes that may affect these parameters.
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 5 of 12 ac test loads and waveforms parameters 3.0v v cc unit r1 22000 ? r2 22000 ? r th 11000 ? v th 1.50 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v th equivalent to: thevenin equivalent all input pulses r th r1
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 6 of 12 switching characteristics over the operating range [10, 11, 12, 13, 14] parameter description 55 ns [14] 70 ns unit min. max. min. max. read cycle t rc read cycle time 55 [14] 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 5 5 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [11, 13] 5 5 ns t hzoe oe high to high z [11, 13] 25 25 ns t lzce ce low to low z [11, 13] 2 5 ns t hzce ce high to high z [11, 13] 25 25 ns t dbe ble / bhe low to data valid 55 70 ns t lzbe ble / bhe low to low z [11, 13] 5 5 ns t hzbe ble / bhe high to high z [11, 13] 10 25 ns t sk [14] address skew 0 10 ns write cycle [12] t wc write cycle time 55 70 ns t sce ce low to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 45 ns t bw ble / bhe low to write end 50 60 ns t sd data set-up to write end 25 45 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [11, 13] 25 25 ns t lzwe we high to low-z [11, 13] 5 5 ns notes: 10. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 1ns/v, timing reference levels of v cc(typ) /2, input pulse levels of 0v to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 11. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedence state. 12. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write 13. high-z and low-z parameters are characterized and are not 100% tested. 14. to achieve 55ns performance, the read access should be ce controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enable going active. for the 70ns cycle, the addresses must be stable within 10ns after the start of the r ead cycle
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 7 of 12 switching waveforms notes: 15. device is continuously selected. oe , ce = v il . 16. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha read cycle 1 (address transition controlled) [14, 15, 16] t sk 50% 50% data valid t rc t ace t doe t lzoe t lzce high impedance t hzoe high oe ce i cc i sb impedanc e address v cc supply current read cycle 2 ( oe controlled) [14, 16] t hzbe bhe / ble t lzbe t hzce data out t dbe t sk
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 8 of 12 notes: 17. data i/o is high impedance if oe > v ih . 18. if chip enable goes inactive with we = v ih , the output remains in a high-impedance state. 19. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data ce address we data i/o oe write cycle 1 (we controlled) bhe / ble t bw [12, 13, 17, 18, 19] don?t care t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data ce address we data i/o oe don?t care write cycle 2 (ce controlled) bhe /ble t bw t sa [12, 13, 17, 18, 19]
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 9 of 12 switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o write cycle 3 (we controlled, oe low) t bw bhe / ble [18, 19] don?t care t hd t sd t sa t ha t aw t wc valid data write cycle 4 (bhe /ble controlled, oe low) [18, 19] t bw t sce t pwe don?t care address ce bhe /ble we data i/o
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 10 of 12 deep sleep mode this mode can be used to lower the power consumption of the psram in an application. in this mode, the data integrity of the psram is not guaranteed. deep sleep mode can be enabled by driving zz low. the device stays in the deep sleep mode until zz is driven high. deep sleep mode?entry/exit [20] deep sleep access timings [21, 22] parameter descrip tion min. max. unit t cdr chip deselect to zz low 0 ns t r operation recovery time 200 s truth table [23] zz ce we oe bhe ble inputs/outputs mode power hhxxxxhigh z deselect/power-down standby (i sb ) h x x x h h high z deselect/power-down standby (i sb ) h l h l l l data out (i/o 0 ?i/o 15 )read active (i cc ) h l h l h l data out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) h l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) h l h h l l high z output disabled active (i cc ) h l h h h l high z output disabled active (i cc ) h l h h l h high z output disabled active (i cc ) h l l x l l data in (i/o 0 ?i/o 15 ) write (upper byte and lower byte) active (i cc ) h l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write (lower byte only) active (i cc ) h l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write (upper byte only) active (i cc ) l h x x h h high z deep power-down deep sleep (i zz ) notes: 20. oe and the data pins are in a ?don?t care? state while the device is in deep sleep mode. 21. all other timing parameters are as shown in the switching characteristics section. 22. t r applies only in the deep sleep mode. 23. h = logic high, l = logic low, x = don?t care. deep sleep mode t r t cdr ce or ble / bhe zz
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 11 of 12 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety a pplications, unless pursuant to an express written agreement with cypress. mobl3 and more battery life are trademarks of cypress semico nductor corporation. all produc t and company names mentioned in this document may be the tradem arks of their respective holders. ordering information speed (ns) ordering code package name package type operating range 55 CYK001M16ZCCAU-FVI55 ba48k 48-ball fine pi tch bga (6 mm 8mm 1.0 mm) industrial 70 cyk001m16zccau-fvi70 ba48k 48-ball fine pi tch bga (6 mm 8mm 1.0 mm) industrial package diagram 48-lead vfbga (6 x 8 x 1 mm) ba48k 51-85150-*b
cyk001m16zccau mobl3? document #: 38-05454 rev. *a page 12 of 12 document history page document title: cyk001m1 6zccau mobl3? 16-mbit (1m x 16) pseudo static ram document number: document #: 38-05454 rev. *a rev. ecn no. issue date orig. of change description of change ** 132407 01/27/04 awk new data sheet *a 220121 see ecn ref changed the datasheet from advanceinformation to final added 55-ns speed bin and address skew restriction for 55-ns speed bin. changed izz from 30ua to 50ua.

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